The high-luminosity phase of operation of the CERN Large Hadron Collider (HL-LHC) will pose new challenges to the detectors and their readout electronics. In particular, the Compact Muon Solenoid (CMS) barrel electromagnetic calorimeter will require a full redesign of the electronic readout chain in order to cope with the increase in luminosity and trigger rate. In this framework, a new application-specific integrated circuit (ASIC) integrating A/D conversion, lossless data compression, and high-speed transmission has been developed and tested. The ASIC, named Lisboa-Torino Ecal Data Transmission Unit (LiTE-DTU), is designed in a commercial CMOS 65-nm process and embeds two 12-bit, 160-MS/s analog-to-digital converters (ADCs), a data selection and compression logic, and a 1.28-Gb/s output serial link. The high-speed 1.28-GHz clock is generated internally from the 160-MHz input by a clock multiplication phase-locked loop (PLL). The circuit has been designed implementing radiation-tolerant techniques in order to work in the harsh environment of the HL-LHC upgrade. The LiTE-DTU is currently in the preproduction phase. A sample of 600 chips has been tested and incorporated into front-end (FE) boards for systems performance testing.

The LiTE-DTU: A Data Conversion and Compression ASIC for the Readout of the CMS Electromagnetic Calorimeter

Argiro, S;Borca, C;Soldi, D;Tedesco, S;
2023-01-01

Abstract

The high-luminosity phase of operation of the CERN Large Hadron Collider (HL-LHC) will pose new challenges to the detectors and their readout electronics. In particular, the Compact Muon Solenoid (CMS) barrel electromagnetic calorimeter will require a full redesign of the electronic readout chain in order to cope with the increase in luminosity and trigger rate. In this framework, a new application-specific integrated circuit (ASIC) integrating A/D conversion, lossless data compression, and high-speed transmission has been developed and tested. The ASIC, named Lisboa-Torino Ecal Data Transmission Unit (LiTE-DTU), is designed in a commercial CMOS 65-nm process and embeds two 12-bit, 160-MS/s analog-to-digital converters (ADCs), a data selection and compression logic, and a 1.28-Gb/s output serial link. The high-speed 1.28-GHz clock is generated internally from the 160-MHz input by a clock multiplication phase-locked loop (PLL). The circuit has been designed implementing radiation-tolerant techniques in order to work in the harsh environment of the HL-LHC upgrade. The LiTE-DTU is currently in the preproduction phase. A sample of 600 chips has been tested and incorporated into front-end (FE) boards for systems performance testing.
2023
70
6
1215
1222
Clocks; Large Hadron Collider; Detectors; Calibration; Readout electronics; Phase locked loops; Iron; Data compression; data conversion; radiation hardening electronics
Mazza, G; Argiro, S; Borca, C; Cometti, S; Cossio, F; Dejardin, M; Dellacasa, G; Mignone, M; Pastrone, N; Soldi, D; Silvestrin, L; Tedesco, S; Tessaro...espandi
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2318/2022810
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