This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be installed during the LHC Long Shutdown 3 (2026–2030). The MOSS chip design is driven by the truly cylindrical detector geometry that imposes that each layer is built out of two wafer-sized, bent silicon chips. The stitching technique is employed to fabricate sensors with dimensions of 1.4 cm × 25.9 cm, thinned to 50 μm. The chip architecture, the in-pixel front-end, the laboratory and in-beam characterisation, the susceptibility to single-event effects, and the series testing are discussed. The testing campaign validates the design of a wafer-scale stitched sensor and the performance of the pixel matrix to be within the ITS3 requirements. The MOSS chip demonstrates the feasibility of the ITS3 detector concept and provides insights for further optimisation and development.

Characterisation of the first wafer-scale prototype for the ALICE ITS3 upgrade: The monolithic stitched sensor (MOSS)

Aglietta, Luca;Alocco, Giacomo;Beolè, Stefania Maria;Kugathasan, Thanushan;Lim, Bong-Hwi;Perciballi, Stefania;Ravasenga, Ivan;Sanna, Isabella;Savino, Umberto;Senyukov, Serhiy;Terlizzi, Livia;
2026-01-01

Abstract

This paper presents the characterisation and testing of the first wafer-scale monolithic stitched sensor (MOSS) prototype developed for the ALICE ITS3 upgrade that is to be installed during the LHC Long Shutdown 3 (2026–2030). The MOSS chip design is driven by the truly cylindrical detector geometry that imposes that each layer is built out of two wafer-sized, bent silicon chips. The stitching technique is employed to fabricate sensors with dimensions of 1.4 cm × 25.9 cm, thinned to 50 μm. The chip architecture, the in-pixel front-end, the laboratory and in-beam characterisation, the susceptibility to single-event effects, and the series testing are discussed. The testing campaign validates the design of a wafer-scale stitched sensor and the performance of the pixel matrix to be within the ITS3 requirements. The MOSS chip demonstrates the feasibility of the ITS3 detector concept and provides insights for further optimisation and development.
2026
1086
1
20
CMOS stitching; Monolithic active pixel sensors; Silicon sensors; Solid state detectors
Abdelrahman, Omar; Rinella, Gianluca Aglieri; Aglietta, Luca; Alocco, Giacomo; Antonelli, Matias; Baccomi, Roberto; Barile, Francesco; Becht, Pascal; ...espandi
File in questo prodotto:
File Dimensione Formato  
1-s2.0-S0168900226000239-main.pdf

Accesso aperto

Tipo di file: PDF EDITORIALE
Dimensione 4.06 MB
Formato Adobe PDF
4.06 MB Adobe PDF Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2318/2122892
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 2
  • ???jsp.display-item.citation.isi??? ND
social impact