Dopant ionization in ultrathin Si films remains poorly investigated at the nanoscale. In this work, independent control of device layer thickness (HSOI) from 30 to 8 nm, dopant concentration (nD) from 1018 to ∼1020 cm−3, and interface quality establishes a systematic framework to discriminate how bulk and interface phenomena affect charge transport in P-doped silicon-on-insulator (SOI) films. When HSOI = 30 nm, transport properties are fully compatible with similarly doped bulk Si. Conversely, when HSOI < 30 nm, a concomitant carrier dose (Ne) and mobility (µe) reduction is observed. This effect, enhanced decreasing nD, is attributed to non-passivated interface states at the Si/SiO2 interface and can be significantly mitigated by rapid thermal oxidation (RTO). Electron-paramagnetic resonance (EPR) and capacitance-voltage (CV) measurements allow the correlation between the quality of the RTO-SiO2/Si interface and electrical properties. After interface engineering, low-temperature electrical characterization revealed a shift of the critical dopant concentration corresponding to the metal-insulator transition and a significant increase in P ionization energy (Ed) in samples with HSOI ≤ 15 nm. These results are discussed considering the dielectric mismatch between Si and SiO2 and the electrostatic confinement within an ultrathin conductive channel, which arises from Si device layer depletion induced by electron trapping at the Si/SiO2 interface.
Interface Effects in Ultrathin Silicon on Insulator Films
Fanciulli M.;
2026-01-01
Abstract
Dopant ionization in ultrathin Si films remains poorly investigated at the nanoscale. In this work, independent control of device layer thickness (HSOI) from 30 to 8 nm, dopant concentration (nD) from 1018 to ∼1020 cm−3, and interface quality establishes a systematic framework to discriminate how bulk and interface phenomena affect charge transport in P-doped silicon-on-insulator (SOI) films. When HSOI = 30 nm, transport properties are fully compatible with similarly doped bulk Si. Conversely, when HSOI < 30 nm, a concomitant carrier dose (Ne) and mobility (µe) reduction is observed. This effect, enhanced decreasing nD, is attributed to non-passivated interface states at the Si/SiO2 interface and can be significantly mitigated by rapid thermal oxidation (RTO). Electron-paramagnetic resonance (EPR) and capacitance-voltage (CV) measurements allow the correlation between the quality of the RTO-SiO2/Si interface and electrical properties. After interface engineering, low-temperature electrical characterization revealed a shift of the critical dopant concentration corresponding to the metal-insulator transition and a significant increase in P ionization energy (Ed) in samples with HSOI ≤ 15 nm. These results are discussed considering the dielectric mismatch between Si and SiO2 and the electrostatic confinement within an ultrathin conductive channel, which arises from Si device layer depletion induced by electron trapping at the Si/SiO2 interface.
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