A 64-channel waveform sampling ASIC for SiPM in space-born applications

The architecture of a 64-channel ASIC for the readout of Silicon Photomultipliers in space experiments is described. Each channel embeds a front-end amplifier with a common gate topology followed by a 256 cells analogue memory with a sampling frequency of 200 MHz. A single memory cell includes a storage capacitor, a single-slope Analog-to-Digital Converter (ADC) with programmable resolution between 8 and 12 bits and the digital control logic. To save power, the A/D conversion is carried-out only when a trigger signal is received. The trigger can either be generated inside the ASIC or provided by an external source. The analogue samples are digitized in parallel, thus reducing the conversion dead time. The memory cells can be arranged in a single array or they can be grouped in shorter slots of 32 or 64 cells that work in a multi-buffer configuration. The channels can work independently or they can be synchronised to acquire the same time-frame in the full chip. The target power consumption is 5 mW/channel. The ASIC is being designed in a 65-nm CMOS technology. A digital-on-top flow is applied for the integration and final validation of the chip. The tape-out is scheduled in the first quarter of 2023.