This work describes the implementation of a 64-channel Application Specific Integrated Circuit (ASIC) developed in a commercial 65 nm CMOS technology to readout the signals collected by a camera plane made of Silicon Photo-Multipliers. The aim of the application is the identification of Extensive Air Showers (EASs) by detecting optical Cherenkov light generated by Ultra-High Energy Cosmic Rays (UHECRs) and Neutrinos (UHENUs) from sub-orbital and orbital altitudes. In this context, the ASIC is designed to store each event into an analog memory based on 256 configurable cells per channel. Then the chip forms a hitmap sent to an Field Programmable Gate Array (FPGA) to recognize a pattern of interest. If the signal is externally validated, the digital conversion can occur on-board using an array of 12-bits Wilkinson analog-to-digital converters (ADCs) at 200 MHz of clock. The readout is realized with two serializers running at 400 MHz in double data rate (DDR). Both the number of cells and the resolution can be configured into partitions of 32, 64 or 256 cells and in the range 8-12 bits respectively, becoming a key feature of this ASIC. The chip submission and testing are planned for the forthcoming months.
The MIZAR ASIC: 64-channel zone-sampling based ASIC for Cherenkov light detection from sub-orbital and orbital altitudes
Salvo, Andrea Di;Garbolino, Sara;Palmieri, Antonio;Rivetti, Angelo;Bertaina, Mario Edoardo
2024-01-01
Abstract
This work describes the implementation of a 64-channel Application Specific Integrated Circuit (ASIC) developed in a commercial 65 nm CMOS technology to readout the signals collected by a camera plane made of Silicon Photo-Multipliers. The aim of the application is the identification of Extensive Air Showers (EASs) by detecting optical Cherenkov light generated by Ultra-High Energy Cosmic Rays (UHECRs) and Neutrinos (UHENUs) from sub-orbital and orbital altitudes. In this context, the ASIC is designed to store each event into an analog memory based on 256 configurable cells per channel. Then the chip forms a hitmap sent to an Field Programmable Gate Array (FPGA) to recognize a pattern of interest. If the signal is externally validated, the digital conversion can occur on-board using an array of 12-bits Wilkinson analog-to-digital converters (ADCs) at 200 MHz of clock. The readout is realized with two serializers running at 400 MHz in double data rate (DDR). Both the number of cells and the resolution can be configured into partitions of 32, 64 or 256 cells and in the range 8-12 bits respectively, becoming a key feature of this ASIC. The chip submission and testing are planned for the forthcoming months.File | Dimensione | Formato | |
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