Research and development activities are ongoing to design the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. In its final implementation the ASIC will incorporate more than lOfe channels. The analog and digital electronics necessary to amplify the detector signal and to digitize the charge information with low power consumption (15 μW/cell) and high dynamic range (up to 100 fC) will be embedded in each channel. Furthermore the area of each read-out cell has to be 100 μm × 100 μm in order to match the pixel sensor grid. To comply with these strict requirements the Time over Threshold (ToT) technique has been employed to extract the analog information. A prototype, named ToPix 2.0, with 320 pixel readout cells, organized in four columns and a simplified version of the end of column readout working at 50 MHz has been already designed and successfully tested. A new prototype is under design, in order to reduce the area of the analog part in the cell, improve its performance and make it compatible with the 155 MHz clock finally chosen by the experiment.
A low power CMOS 0.13µm high dynamic range front-end for 100µm × 100µm pixel sensors
KUGATHASAN, THANUSHAN
2010-01-01
Abstract
Research and development activities are ongoing to design the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. In its final implementation the ASIC will incorporate more than lOfe channels. The analog and digital electronics necessary to amplify the detector signal and to digitize the charge information with low power consumption (15 μW/cell) and high dynamic range (up to 100 fC) will be embedded in each channel. Furthermore the area of each read-out cell has to be 100 μm × 100 μm in order to match the pixel sensor grid. To comply with these strict requirements the Time over Threshold (ToT) technique has been employed to extract the analog information. A prototype, named ToPix 2.0, with 320 pixel readout cells, organized in four columns and a simplified version of the end of column readout working at 50 MHz has been already designed and successfully tested. A new prototype is under design, in order to reduce the area of the analog part in the cell, improve its performance and make it compatible with the 155 MHz clock finally chosen by the experiment.
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