VHDL design of digital adaptive filters for PANDA signal processing

The PANDA (antiProton ANnihilation in Darmstadt) experiment at the new Facility for Antiproton and Ion Research (FAIR) will study interactions between protons and antiprotons in the momentum range 1.5-15 GeV/c. The physics program is very demanding and requires an efficient and flexible triggering system that can handle a data rate in the range 40 to 200 GB/s due to an interaction rate of over 10 MHz. A Serial-Peripheral-Interface firmware was fully developed and implemented in VHDL to interface clocks on-board the digital processing unit and the connected ADC/DAC modules. Running operation was tested successfully. Digital least mean square (LMS) adaptive filters were designed and implemented for real-time filtering in data acquisition at work frequencies higher than 100 MHz to cope the foreseen high rate of PANDA experiment.