In this paper we advocate the Loop-of-stencil- reduce pattern as a way to simplify the parallel programming of heterogeneous platforms (multicore+GPUs). Loop-of-Stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop. It transparently targets (by using OpenCL) combinations of CPU cores and GPUs, and it makes it possible to simplify the deployment of a single stencil computation kernel on different GPUs. The paper discusses the implementation of Loop-of-stencil-reduce within the FastFlow parallel framework, considering a simple iterative data-parallel application as running example (Game of Life) and a highly effective parallel filter for visual data restoration to assess performance. Thanks to the high-level design of the Loop-of-stencil-reduce, it was possible to run the filter seamlessly on a multicore machine, on multi-GPUs, and on both.

The Loop-of-Stencil-Reduce paradigm

ALDINUCCI, MARCO;DROCCO, MAURIZIO;
2015-01-01

Abstract

In this paper we advocate the Loop-of-stencil- reduce pattern as a way to simplify the parallel programming of heterogeneous platforms (multicore+GPUs). Loop-of-Stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop. It transparently targets (by using OpenCL) combinations of CPU cores and GPUs, and it makes it possible to simplify the deployment of a single stencil computation kernel on different GPUs. The paper discusses the implementation of Loop-of-stencil-reduce within the FastFlow parallel framework, considering a simple iterative data-parallel application as running example (Game of Life) and a highly effective parallel filter for visual data restoration to assess performance. Thanks to the high-level design of the Loop-of-stencil-reduce, it was possible to run the filter seamlessly on a multicore machine, on multi-GPUs, and on both.
2015
International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara)
Helsinki, Finland
August 20-22, 2015
Proc. of Intl. Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms (RePara)
IEEE
172
177
978-146737951-9
978-1-4673-7952-6
fastflow
Marco Aldinucci; Marco Danelutto; Maurizio Drocco; Peter Kilpatrick; Guilherme Peretti Pezzi; Massimo Torquati
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2318/1523738
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